1. Field of the Invention
The present invention relates to a wiring board on which semiconductor chips are mounted, and to a method of manufacturing a semiconductor device that uses the wiring board.
2. Description of the Related Art
Conventionally, a MAP (Mold Array Process) method is used as a method of manufacturing a BGA (Ball Grid Array) type semiconductor device. According to the MAP method, a semiconductor chip is mounted on each of a plurality of product formation sections defined on a wiring board, a sealing body that integrally covers the plurality of product formation sections is formed on the wiring board, and thereafter the wiring board is divided into respective product formation sections (for example, see JP2001-044324A or JP2001-044229A).
A wiring board has a product formation area in which a plurality of product formation sections on which semiconductor chips are mounted are arranged, and a molding area on which a sealing resin material is provided as a sealing body that covers the semiconductor chips mounted on the product formation area. A wiring pattern that is electrically connected to the semiconductor chips is formed in the product formation area. The molding area is arranged all along the circumference of the product formation area. The wiring board also has a clamp area at which the wiring board is sandwiched and held between an upper die and a lower die of a molding die when forming the sealing resin material in the molding area. The clamp area is arranged on the outer circumferential side of the molding area, and is formed in a frame shape along an outer circumferential portion of the wiring board.
To increase the rigidity of the wiring board and suppress the occurrence of warping, a solid pattern is provided on an outer circumferential side of the product formation sections on which a desired wiring pattern is formed. The solid pattern is formed by completely covering the relevant area with the material used to form the wiring. The solid pattern is formed so as to extend across the molding area and the clamp area of the wiring board.
However, when a solid pattern is formed so as to continuously cover, in other words, completely cover, one face of a wiring board, there is the disadvantage that warping occurs in the thickness direction of the wiring board due to a difference in the coefficients of thermal expansion between the material forming the solid pattern and the material forming the wiring board. Further, when a solid pattern is formed so as to completely cover one face of a wiring board, there is the disadvantage that the solid pattern peels off from the wiring board.
Therefore, to alleviate warping that occurs in the wiring board and suppress peeling of the solid pattern, the solid pattern is divided into a plurality of dots that are formed in a predetermined size, and the plurality of dots are arranged in a matrix form. Further, the dots comprising the solid pattern are formed in a predetermined size so that warping that occurs in the wiring board due to the solid pattern decreases to a certain extent.
Furthermore, in the clamp area, a gate area is provided at a position that corresponds to a gate of the molding die. The gate area is formed by completely covering the relevant area with the material used to form the wiring, and in order to ensure releasability with respect to the sealing resin material, an insulating film is removed from the gate area.
Recently, accompanying the miniaturization and thinning of portable electronic equipment, there has also been a demand for miniaturization and thinning of semiconductor devices that are mounted in such portable electronic equipment, and consequently wiring boards are also being made thinner. When the thickness of a wiring board is reduced to around 0.1 mm, the mechanical rigidity of the wiring board significantly decreases.
Consequently, in a process for molding a wiring board, as shown in FIG. 1, when an outer circumferential portion of a thin wiring board 101 is sandwiched and held across clamp area 113 between a set of upper die 121a and lower die 121b that comprise molding die 121, there is the problem that a portion of gate area 114 that is within clamp area 113 and that corresponds to gate 124 of molding die 121 is deformed by a force that pinches wiring board 101 of molding die 121.
When the portion of gate area 114 is deformed so as to bulge towards the side of cavity 122 of molding die 121 in this manner, there is a risk that sealing resin material 130 that is injected into the inside of molding die 121 will flow from one surface side of wiring board 101 to another surface side of wiring board 101 and leak out, and that sealing resin material 130 will cover a land that is formed on the rear surface side of wiring board 101. Consequently, it will not be possible to form solder balls on the land of the wiring board in a ball mounting process that is performed thereafter in the semiconductor device manufacturing process. There is thus the problem that defective semiconductor devices will be manufactured, and it will not be possible to mount the semiconductor devices on a mounting board.